The present invention relates to a method of fabricating a semiconductor device in which at least a lightly doped type (hereinafter, referred to as "LDD type") insulated-gate field-effect transistor and a bipolar transistor are formed on a common base substrate.
For example, a semiconductor device, in which LDD type insulated-gate field-effect transistors and bipolar transistors are formed on a common semiconductor base substrate, is used typically for a frequency converter of a communication system. In this case, if the bipolar transistor is configured as a bipolar transistor for high-frequency application, such a bipolar transistor is required to be operated at a high-speed. To achieve high-speed operation of the bipolar transistor, it is important to shorten a base transit-time due to shallow junction of a base of the bipolar transistor and reduce the resistance of the base.
In the case of forming a base of a bipolar transistor in accordance with a known ion implantation process, however, it is difficult to realize shallow junction of the base because of a problem of a channeling tail of an impurity concentration profile, and further, if ions of an impurity are heavily implanted to reduce the resistance of the base, there arises another problem of crystal defects caused by damages occurring upon ion implantation.
To solve the above problems, it has been known to form a base layer of a bipolar transistor in accordance with an epitaxial base technology. The epitaxial base technology, in which a high-concentration base layer having a thickness of about 50 nm can be accurately formed by epitaxial growth, becomes a focus of attention as a key technology for realizing a high-speed bipolar transistor.
In actual, a high-speed bipolar transistor exhibiting the maximum cutoff frequency being more than 50 GHz has been realized in accordance with the epitaxial base technology.
Further, a heterojunction bipolar transistor (hereinafter, referred to as "HBT") suitable for higher-speed operation can be realized by forming an epitaxial base layer made from SiGe being narrower in band gap than Si.
The performances required for a bipolar transistor, however, include not only the above high-speed operation characteristic but also a high-power amplification factor and a high-withstand voltage. The latter performances are typically required for a bipolar transistor used for a power circuit and a bipolar transistor used for a drive circuit of a cathode-ray tube (CRT).
From this viewpoint, the formation of the above-described high-concentration base layer, which is important to realize a high-speed bipolar transistor, has the following disadvantages:
(1) A current amplification factor .beta. is reduced because of a reduction in emitter injection efficiency and thereby an emitter storage time .tau..sub.e is increased. PA1 (2) A field strength is increased because of an increase in junction concentration between the emitter and the base and thereby a withstand voltage BV.sub.ebo between the emitter and the base is reduced.
Accordingly, if a bipolar transistor is used for an application requiring a high current amplification factor (high .beta.) and a high withstand voltage (high BV.sub.ebo), it is rather undesirable to make the concentration of a base layer of the bipolar transistor high. In other words, it is desirable to form a low-concentration base layer of the bipolar transistor used for such application not by the epitaxial base technology but by the usual ion implantation process.
Conventionally, since a method capable of carrying out the process of forming a bipolar transistor by the epitaxial base technology simultaneously with the process of forming a bipolar transistor by the usual ion implantation in such a manner that both the processes are matched to each other has not been established, it has been difficult to form both the bipolar transistors on a common semiconductor base substrate.
As a result, conventionally, a circuit including a bipolar transistor requiring high-speed operation and a circuit including a bipolar transistor requiring a high-current amplification factor and a high-withstand voltage have been formed as separate chips.
To be more specific, in the case of manufacturing a communication system including a frequency converter circuit requiring high speed operation, and a drive circuit for a CRT and an input/output circuit to an external memory requiring a high-current amplification factor and a high-withstand voltage, it has been required to provide the step for individually assembling chips including these circuits in the system and the step for connecting the chips to each other by way of wiring. This causes a problem in complicating the assembling steps of the system, thereby raising the manufacturing cost of the system.
A technology for solving the above problem has been disclosed, for example, in Japanese Patent Application No. Hei 9-133482 (Japanese Patent Laid-open No. Hei 10-321730) In accordance with this technology, a relatively low concentration base layer for a bipolar transistor requiring a high current amplification factor and a high withstand voltage is formed in an opening of a silicon nitride film formed on the surface of an n-type epitaxial layer, and a relatively high concentration and shallow junction base layer for a high-speed bipolar transistor is formed in another opening of the silicon nitride film by selective epitaxial growth.
In accordance with the related art method for fabricating a bipolar transistor, however, it has been difficult to realize a system-on-chip as a so-called BiCMOS transistor circuit in which a complementary type insulated-gate transistor, that is, so-called CMOS being high in packaging density and low in power consumption is combined with a bipolar transistor circuit.
This is because, for popularization of the BiCMOS transistor circuit, it becomes important not only to increase the performance of the BiCMOS transistor circuit but also to reduce the number of fabrication steps of the circuit for lowering the fabrication cost thereof.
From this viewpoint, the combination of a CMOS transistor circuit, in which the aspect ratio (stepped height of vertical structure/lateral dimension) becomes larger along with the trend toward finer-geometries, with a bipolar transistor of a double-polysilicon structure having a large stepped portion in the vertical direction because a base layer and an emitter layer are stacked in the vertical direction, causes a problem in complicating the wiring step thereby raising the fabrication cost.
The related art method of fabricating a bipolar transistor, in which a base layer of a high-speed bipolar transistor is formed by using a selective epitaxial technology, has another problem that since the selective epitaxial technology has a complicated reaction mechanism, it is difficult to perfectly suppress the formation of nuclei on an insulating film and form an epitaxial layer with a good crystallinity on a silicon substrate with a high controllability and a high production yield.